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WCMB2016R4X
128K x 16 Static RAM
Features
* Low voltage range: -- 1.65V-1.95V * Ultra-low active power -- Typical Active Current: 0.5 mA @ f = 1 MHz * * * * -- Typical Active Current: 1.5 mA @ f = fmax Low standby power Easy memory expansion with CE and OE features Automatic power-down when deselected CMOS for optimum speed/power and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table at the back of this data sheet for a complete description of read and write modes. The WCMB2016R4X is available in a 48-ball FBGA package.
Functional Description
The WCMB2016R4X is a high-performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This device is ideal for portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE HIGH or both BLE
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
128K x 16 RAM Array 2048 X 1024
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER
BHE WE CE OE BLE CE BHE BLE
A12
A11
A13
A14 A15
Power -Down Circuit
A16
WCMB2016R4X
Pin Configuration[1, 2]
FBGA Top View 1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC 2 OE BHE I/O10 I/O11 3 A0 A3 A5 NC 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 Vccq Vssq I/O6 I/O7 NC A B C D E F G H
I/O12 DNU I/O13 NC A8 A14 A12 A9
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied.................................................. -55C to +125C Supply Voltage to Ground Potential .................-0.2V to +2.4V
DC Voltage Applied to Outputs in High Z State[3]........................................ -0.2V to VCC + 0.2V DC Input Voltage[3].................................... -0.2V to VCC + 0.2V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA
Operating Range
Device WCMB2016R4X Range Industrial Ambient Temperature -40C to +85C VCC 1.65V to 1.95V
Product Portfolio
Power Dissipation (Industrial) Product VCC Range VCC(min.) VCC(typ.)[4] VCC(max.) WCMB2016R4X 1.65V 1.80V 1.95V 70 ns Speed Operating (ICC) f = 1MHz Typ.[4] 0.5 mA Max. 2 mA f = fmax Typ.[4] 1.5 mA Max. 6 mA Standby (ISB2) Typ.[4] 1 A Max. 8 A
Notes: 1. NC pins are not connected to the die. 2. E3 (DNU) can be left as NC or Vss to ensure proper application. 3. VIL(min) = -2.0V for pulse durations less than 20 ns. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C.
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WCMB2016R4X
Electrical Characteristics Over the Operating Range
WCMB2016R4X Parameter VOH VOL VIH VIL IIX IOZ Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current GND < VI < VCC Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current-- CMOS Inputs Automatic CE Power-Down Current-- CMOS Inputs GND < VO < VCC, Output Disabled f = fMAX = 1/tRC
f = 1 MHz
Test Conditions IOH = -0.1 mA IOL = 0.1 mA VCC = 1.65V VCC = 1.65V
Min. 1.4
Typ.[4]
Max. 0.2
Unit V V V V A A mA mA
1.4 -0.2 -1 -1 1.5 0.5
VCC + 0.2V 0.4 +1 +1 6 2
ICC
VCC = 1.95V IOUT = 0 mA CMOS levels
ISB1
CE > VCC-0.2V, VIN>Vcc-0.2V, VIN<0.2V f = fMAX (Address and Data Only), f=0 (OE, WE, BHE and BLE) CE > VCC-0.2V VIN > VCC-0.2V or VIN < 0.2V, f = 0, Vcc=1.95V
1
8
A
ISB2
Capacitance[5]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC= VCC(typ) Max. 6 8 Unit pF pF
Thermal Resistance
Description Thermal Resistance (Junction to Ambient)[5] Thermal Resistance (Junction to Case)[5]
Note: 5. Tested initially and after any design or process changes that may affect these parameters.
Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board
Symbol JA JC
BGA 55 16
Units C/W C/W
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WCMB2016R4X
AC Test Loads and Waveforms
R1 VCC OUTPUT GND 30 pF INCLUDING JIG AND SCOPE R2 Rise Time: 1 V/ns Fall Time: 1 V/ns VCC Typ 10% ALL INPUT PULSES 90% 90% 10%
Equivalent to:
THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters R1 R2 RTH VTH
1.8V 13500 10800 6000 0.80
UNIT Ohms Ohms Ohms Volts
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR tCDR[5] tR[6] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = 1.0V CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V 0 tRC Conditions Min. 1.0 0.5 Typ.[4] Max. 1.95 5 Unit V A ns ns
Data Retention Waveform[7]
DATA RETENTION MODE VCC
VCC(min.)
tCDR
VDR > 1.0 V
VCC(min.)
tR
CE or BHE.BLE
Notes: 6. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
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WCMB2016R4X
Switching Characteristics Over the Operating Range[8]
WCMB2016R4X Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low CE LOW to Low Z[9] Z[9] Z[9, 10] 0 70 70 5 25 70 60 60 0 0 50 60 30 0 25 10 5 25 10 25 OE HIGH to High Z[9, 10] CE HIGH to High 10 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Unit
CE LOW to Power-Up CE HIGH to Power-Down BLE / BHE LOW to Data Valid BLE / BHE LOW to Low Z[9] Z[9, 10] BLE / BHE HIGH to High Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width BLE / BHE LOW to Write End Data Set-Up to Write End Data Hold from Write End WE LOW to High Z
[9, 10] [9]
WRITE CYCLE[11]
WE HIGH to Low Z
Note: 8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH and 30 pF load capacitance. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. tHZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high impedence state. 11. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE =VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
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WCMB2016R4X
Switching Waveforms
[12, 13]
Read Cycle No. 1(Address Transition Controlled)
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID
[13, 14]
tAA DATA VALID
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE tACE OE
tRC tPD tHZCE
BHE/BLE
tDOE
tHZOE
tLZOE tHZBE
tDBE
tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% DATA VALID
HIGH IMPEDANCE
ICC ISB
Notes: 12. Device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE, BHE, BLE, transition LOW.
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WCMB2016R4X
Switching Waveforms
Write Cycle No. 1 (WE Controlled)
[11, 15, 16]
tWC ADDRESS tSCE CE tAW WE tSA tPWE tHA
BHE/BLE
tBW
OE tSD DATA I/O NOTE 17 tHZOE DATAIN VALID tHD
Write Cycle No. 2 (CE Controlled) [11, 15, 16]
tWC ADDRESS tSCE CE
tSA
tAW tPWE
tHA
WE
BHE/BLE
tBW
OE tSD DATA I/O NOTE 17 tHZOE DATAIN VALID tHD
Note: 15. Data I/O is high impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 17. During this period, the I/Os are in output state and input signals should not be applied.
7
WCMB2016R4X
Switching Waveforms
Write Cycle No. 3 (WE Controlled, OE LOW)
[16]
tWC ADDRESS tSCE CE
BHE/BLE tAW tSA WE
tBW
tHA tPWE
tSD DATAI/O NOTE 17 tHZWE DATAIN VALID
tHD
tLZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
[16]
tWC ADDRESS
CE tSCE tAW BHE/BLE tSA WE tPWE tSD DATA I/O NOTE 17 DATAIN VALID tHD tBW tHA
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WCMB2016R4X
Typical DC and AC Characteristics
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ) Typ, TA = 25C.)
Operating Current vs. Supply Voltage 2.4 ICC (mA) 2.0 ISB (A) 1.6 1.2 0.8 0.4 0.0 1.65 1.80 SUPPLY VOLTAGE (V) (f = 1 MHz) (f=fmax) Standby Current vs. Supply Voltage 3.5 3.0 2.0 1.5 1.0 0.5 0 1.95 1.65 1.80 1.95 SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage 40 35 30 TAA (ns) 25 20 15 10 1.65 1.8 SUPPLY VOLTAGE (V) 1.95
Truth Table
CE H X L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X H L H L L H L L H L BLE X H L L H L L H L L H Inputs/Outputs High Z High Z Data Out (I/OO-I/O15) Data Out (I/OO-I/O7); I/O8-I/O15 in High Z Data Out (I/O8-I/O15); I/O0-I/O7 in High Z High Z High Z High Z Data In (I/OO-I/O15) Data In (I/OO-I/O7); I/O8-I/O15 in High Z Data In (I/O8-I/O15); I/O0 -I/O7 in High Z Mode Deselect/Power-Down Deselect/Power-Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
9
WCMB2016R4X
Ordering Information
Speed (ns) 70 Ordering Code WCMB2016R4X-FF70 Package Name FB48A Package Type 48-Ball Fine Pitch BGA Operating Range Industrial
Package Diagrams 48-Ball (6.0 mm x 8.0 mm x 1.0 mm) Fine Pitch BGA, FB48A
Top View Bottom View
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WCMB2016R4X
Document Title: WCMB2016R4X, 128K x 16 Static RAM REV. ** Spec # 38-14011 ECN # 115226 Issue Date 4/24/2002 Orig. of Change MGN Description of Change New Data Sheet
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